1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv4522 features processed with hvcmos ? technology output voltages to -220v source current minimum 60ma shift register speed 8.0mhz polarity and blanking inputs cmos compatible inputs forward and reverse shifting options can be used with the hv5522 to prov ide 220v push-pull operation 44-lead plcc surface mount package ? ? ? ? ? ? ? ? ? functional block diagram 32-channel serial to parallel converter with p-channel open drain outputs general description the hv4522 is a low-voltage serial to high-voltage parallel converter with p-channel open drain outputs. this device has been designed for use a driver for ac-electroluminescent displays. it can also be used in any application requiring multiple output high-voltage current source capabilities, such as driving inkjet and electrostatic print heads, plasma panels, or vacuum ?uorescent displays. this device consists of a 32-bit shift register, 32 data latches, and control logic to perform polarity and blanking functions. data is shifted through the shift register on the logic high-to- low transition of the clock. the hv4522 shifts in the counter clockwise direction (when viewed from the top of the package). a data output buffer is provided for cascading devices. this output re?ects the current status of the last bit of the shift register. the data in the shift register is latched when the latch enable pin is brought to logic high, and then returned to ground. if the latch enable pin is held high, the latch becomes transparent and the shift register data is directly re?ected in the outputs. for applications requiring active pull down as well as pull up, the hv4522 can be paired with the hv5522. polarity blanking latch enabl e data input cloc k data ou t hv ou t 1 (outputs 3 to 30 not shown ) latch latch hv ou t 2 hv ou t 31 hv ou t 32 latch latch vs s 32-bi t shift registe r
2 hv4522 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com absolute maximum ratings parameter value supply voltage, v dd +0.5v to -16v output voltage , v pp +0.5v to -240v logic input levels +0.5v to v dd -0.3v ground current (1) 1.5a continuous total power dissipation (2) 1200mw operating temperature range -40c to +85c storage temperature range -65c to +150c lead temperature (1.6mm from case for 10 seconds) 260c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to v ss . notes: duty cycle limited by the total power dissipated in the package. for operation above 25c ambiant derate linearly to maximum operating temperature at 20mw/c. 1. 2. recommended operating conditions sym parameter min max units v dd logic supply voltage -10.8 -13.2 v v pp output voltage +0.3 -220 v v ih high-level input voltage (logic 1) v dd +2.0v v dd v v il low-level input voltage (logic 0) 0 -2.0 v f clk clock frequency - 8.0 mhz t a operating free-air temperature -40 +85 c note: all voltages are referenced to v ss pin con?guration product marking 44-lead plcc (pj) yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top marking top marking bottom marking yyww hv4522pj llllllllll ccccccccccc aaa 1 44 6 40 44-lead plcc (pj) (top view) ordering information device package option 44-lead plcc .653x.653in body .180in height (max) .050in pitch hv4522 hv4522pj-g -g indicates package is rohs compliant (green)
3 hv4522 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com dc electrical characteristics (over recommended operating conditions unless otherwise noted) sym parameter min max units conditions i dd v dd supply current - -15 ma f clk = 8.0mhz, f data = 4.0mhz i ddq quiescent v dd supply current - -100 a v in = v ss or v dd i o(off) off state output current - -100 a all sws parallel i ih high-level logic input current - -1.0 a v ih = v dd i il low-level logic input current - +1.0 a v il = v ss v oh high level output data out v dd +1.0v - v i dout = -100 a v ol low level output hv out - -30 v i hvout = -60ma d out - -1.0 v i dout = -100 a v oc hv out clamp voltage - +1.5 v i ol = +60ma ac electrical characteristics (v dd = -12v, t c = 25c) sym parameter min max units conditions f clk clock frequency - 8.0 mhz --- t wh /t wl clock width high or low 62 - ns --- t su data set-up time before clock rises 50 - ns --- t h data hold time after clock rises 20 - ns --- t on turn on time, hv out from enable - 400 ns r l = 10k to v oo max t dhl delay time clock to data high to low - 100 ns c l = 15pf t dlh delay time clock to data low to high - 100 ns c l = 15pf t dle delay time clock to le high to low 50 - ns --- t wle le pulse width 50 - ns --- t sle le set-up time before clock rises 50 - ns --- input and output equivalent circuits v ss input hv out logic inputs data ou t logic data output high voltage output v dd v ss v dd v ss
4 hv4522 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com switching waveforms latch enabl e d ata vali d 50% 50% d ata inpu t cloc k 50% 50% 50 % t su t h t wh t wl 50 % 50 % t dhl t dlh 50 % t wl e t dle t sl e 50 % 50 % t on hv out w/ s/r high 10 % v ss v ss -1 2 v ss v ss -1 2 v ss v ss -1 2 v ss v ss -1 2 v ss v ss -1 2 v ss v oo d ata ou t function table function inputs outputs data clk le bl pol shift reg hv outputs data out * 1 2...32 1 2...32 all on x x x l l * *...* h h...h * all off x x x l h * *...* l l...l * invert mode x x l h l * *...* * *...* * load s/r h or l l h h h or l *...* * *...* * load latches x h or l h h * *...* * *...* * x h or l h l * *...* * *...* * transparent latch mode l h h h l *...* l *...* * h h h h h *...* h *...* * notes: h = high level = -12v, l = low level = 0v, x = irrelevant, = high-to-low transition, = low-to-high transition. * = dependent on previous stages state before the last clk high-to-low transition or last le high.
5 hv4522 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # function description 1 hv out 17 high voltage outputs. 2 hv out 18 3 hv out 19 4 hv out 20 5 hv out 21 6 hv out 22 7 hv out 23 8 hv out 24 9 hv out 25 10 hv out 26 11 hv out 27 12 hv out 28 13 hv out 28 14 hv out 30 15 hv out 31 16 hv out 32 17 n/c no connect. 18 data out data output pin. 19 n/c no connect. 20 n/c 21 n/c 22 pol inverts the polarity of the hv out pins 23 clk clock pin, shift registers shifts data on rising edge of input clock. 24 vss reference voltage, usually ground. 25 vdd logic supply voltage. 26 le logic enable pin, data is shifted from shift register to latches on logic input low . 27 data in data input pin. 28 bl blanking pin, logic input low sets all hv out pins low. 29 hv out 1 high voltage outputs. 30 hv out 2 31 hv out 3 32 hv out 4 33 hv out 5 34 hv out 6 35 hv out 7 36 hv out 8 37 hv out 9 37 hv out 10 39 hv out 11 40 hv out 12 41 hv out 13 42 hv out 14 43 hv out 15 44 hv out 16 pin description
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2008 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 9408 9 te l: 408-222-8888 www .supertex.com 6 hv4522 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv4522 a092508 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc nom .172 .105 - - - .690 .653 .690 .653 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension is a non-jedec dimension. drawings not to scale. supertex doc. #: dspd-44plccpj, version d092408. .150 ma x .048/.042 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew horizontal side v iew v iew b a a2 a1 seating plane e b note 1 (index area) .056/.042 x 45 o .020max (3 places) .020 min ve rtical side v iew v iew b note 2 44 b1 base plane notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. actual shape of this feature may vary. 1. 2.
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